///////////////////////////////////////////////////////////////////////////////
// Company: University of Cincinnati
// Author: Jordan Ross, Ben Gentry, Bryan Butsch
//
// Created Date: 09/22/2013
// Design Name:
// Module Name: top_level
// Project Name: top_level
// Target Devices: Cyclone II EP2C20F484C7
// Tool Versions: Quartus 13.0
// Description: This module instantiates a bare processor, a memory unit, and
//    a counter to cycle through memory addresses.
// 
// Dependencies: proc.v
//               memory.v
//               counter.v
// 
// Revision:
// 0.01 - File Created
//
// Additional Comments:
//
///////////////////////////////////////////////////////////////////////////////
module top_level #(parameter width=9)(
    input MClock,           // Memory Clock
    input PClock,           // Processor Clock
    input Resetn,           // Reset Signal
    input Run,              // Run Signal
    output [width-1:0]Bus,  // 9-bit Bus
    output Done             // Done Signal
    //output ErrorLED         // Error Indicators
    );
	
	wire [width-1:0] Data; // Output of memory block
	wire [4:0] Addr; // Output of counter - equates to address value in memory block
	
    // Instantiate the counter module
	counter count(
		.MClock		(MClock),
		.Resetn		(Resetn),
		.n				(Addr)
	);
    
    // Instantiate the memory module
	memory mem(
		.address		(Addr),
		.clock		(MClock),
		.q				(Data)
	);
	
	// Instantiate the processor module
	Proc processor(
		.DIN			(Data),
		.Resetn		(Resetn),
		.Clock		(PClock),
		.Run			(Run),
		.Done			(Done),
		.BusWires	(Bus)
		/*.ErrorLED (ErrorLED)*/
	);
	
endmodule

